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dc.contributor.advisorLoomis, Herschel H., Jr.
dc.contributor.advisorRoss, Alan A.
dc.contributor.authorYuan, Rong
dc.dateDecember 2003
dc.date.accessioned2012-03-14T17:47:49Z
dc.date.available2012-03-14T17:47:49Z
dc.date.issued2003-12
dc.identifier.urihttp://hdl.handle.net/10945/6116
dc.description.abstractWithout the protection of atmosphere, space systems have to mitigate radiation effects. Several different technologies are used to deal with different radiation effects in order to keep the space device work properly. One of the radiation effects called Single Event Upset (SEU) can change the state of a component or data on the bus. A single error is possible to cause a system failure if it is not corrected. Besides error correction, a space system also needs the flexibility to be modified or upgraded easily. Consequently, the idea of having a TMR design instantiated in an FPGA to construct a Configurable Fault-Tolerant Processor (CFTP) developed. The TMR, which runs one program in three identical soft-core processors with voters, is a scheme used to mitigate an SEU. The full design of TMR running in an FPGA functions as a System-On-a-Chip (SOC). Both soft-core processor and FPGA offer the CFTP a great flexibility to be reconfigured. A complete TMR design includes some fundamental components besides processors and voters such as the Reconiler, Interrupt, and Error Syndrome Storage Device (ESSD). These components have their unique function in the TMR design. They are created and simulated. Factors that affect test bench-settings like processor pipelining are important to always keep in mind. A component is designed to implement proper functions first. Then it is revised to work with the processor and memory. The full design for the TMR in this thesis proves its ability to detect and correct an SEU. The follow-on research suggested is to improve the efficiency and performance of this design.en_US
dc.description.urihttp://archive.org/details/triplemodularred109456116
dc.format.extentxxii, 261 p. : ill. (some col.)en_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsCopyright is reserved by the copyright owneren_US
dc.subject.lcshArtificial satellitesen_US
dc.subject.lcshEffect of radiation onen_US
dc.subject.lcshAtmospheric radiationen_US
dc.subject.lcshAstronautical instrumentsen_US
dc.titleTriple modular redundancy (TMR) in a configurable fault-tolerant processor (CFTP) for space applicationsen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical and Computer Engineering
dc.subject.authorSingle event upseten_US
dc.subject.authorSEUen_US
dc.subject.authorConfigurable fault-tolerant processoren_US
dc.subject.authorCFTPen_US
dc.subject.authorTMRen_US
dc.subject.authorFPGAen_US
dc.subject.authorSystem-on-a-chipen_US
dc.subject.authorSOCen_US
dc.subject.authorReconcileren_US
dc.subject.authorInterrupt and error syndrome storage deviceen_US
dc.subject.authorESSDen_US
dc.description.serviceFirst Lieutenant, Republic of China (Taiwan) Air Forceen_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.verifiednoen_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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