Two-Phase Dynamic Logic Circuits for Gallium Arsenide Complementary HIGFET Fabrication

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Author
Fouts, Douglas Jai
Shehata, Khaled Ali
Date
1999-07-20Metadata
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A two-phase dynamic logic circuit for complementary GaAs
HIGFET fabrication processes has a precharge transistor
connected between a precharge voltage source and an output
node of the logic circuit. The precharge transistor is controlled
by a clock signal such that the output node precharges
when the clock signal is low and is isolated from the
precharge voltage source when the clock signal is high. An
evaluate transistor connected to the output node and an
NFET logicock has a first terminal connected to the
evaluate transistor such that the evaluate transistor is
between the NFET logicock and the output node. A
second terminal of the logicock is connected to a voltage
source and a data input terminal that is arranged to receive
data input signals. The NFET logicock includes on or
more transistor(s) is arranged to generate a logic value. The
evaluate transistor is controlled by the clock signal such that
when the clock signal is low, the output node is isolated form
the NFET logicock, and when the clock signal is high, the
logic value generated by the logicock is allowed to
determine the voltage on the output node of the logic circuit.
A pass-gate is arranged to receive an input signal and
conditionally pass the input signal to the gate(s) of the
transistor(s) in the NFET logicock under the control of the
clock signal such that the input is allowed to influence the
gate voltage of the evaluation transistor when the clock
signal is low, but is not allowed to influence the gate voltage
of the transistor(s) in the logicock when the clock signal
is high.
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This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.Collections
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