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dc.contributor.advisorFouts, Douglas J.
dc.contributor.authorGedra, David R.
dc.dateMarch 1995
dc.date.accessioned2012-07-31T19:54:03Z
dc.date.available2012-07-31T19:54:03Z
dc.date.issued1995-03
dc.identifier.urihttp://hdl.handle.net/10945/7532
dc.description.abstractCharge coupled devices (CCDs) are semiconductor devices which can transfer information, represented by a quantity of electrical charge, from one physical location of the semiconductor substrate to another in a controlled manner with the use of properly sequenced clock pulses. These devices can be applied to imaging, signal processing, logic, and digital storage applications. In this thesis, the design of an electrically stimulated CCD analog delay line, using the design tools currently available at the Naval Postgraduate School, is reported on. The major issues addressed are the electrode gate structure and composition, charge confinement techniques, and clocking schemes. Additionally, techniques for inpuning and detecting charge packets from the CCD register are examined. The Metal Oxide Semiconductor Integration Service (MOSIS) design rules only permit Bulk Channel Charge Couple Devices (BCCDs) to be lald out, and not Surface Channel Charge Coupled Devices (SCCDs). Restricted to a die size of 2.24 mm length, the electrode gates were chosen to be polysilicon polysilicon 8 micron length with 2 micron overlap and 20 micron width, giving the BCCD 64 stages. An on chip four phase clocking circuit with output drivers on each phase provides the control voltage for the gate electrodes. The small width of the BCCD delay line utilizes only a small portion of the available 2.22 mm die width. Therefore, four different BCCDs were designed in the layout. Two of the BCCDs have a p-diffusion stop to contain the charge laterally as it propagates along the channel while two BCCDs do not. Additionally, two of the BCCDs utilize the charge partition input technique with three control gates and two BCCDs use the dynamic current injection with one control gate.en_US
dc.description.urihttp://archive.org/details/designofvlsichar109457532
dc.format.extent101 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.titleDesign of a VLSI charge-coupled device analog delay lineen_US
dc.typeThesisen_US
dc.contributor.departmentElectrical Engineering
dc.description.serviceU.S. Navy (U.S.N.) author.en_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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