A CMOS current-mode full-adder cell for multi-valued logic VLSI
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Authors
Barton, Robert James
Subjects
Advisors
Fouts, Douglas J.
Zaky, Amr
Date of Issue
1995-09
Date
September 1995
Publisher
Monterey, California. Naval Postgraduate School
Language
en_US
Abstract
This thesis describes the design and implementation of a carry save adder cell for multivalued logic VLSI. A four valued system was chosen and the logic was analyzed and minimized using the HAMLET CAD tool. SPICE was used to design and simulate the required behavior of the current mode CMOS circuits. A VLSI test and evaluation integrated circuit was implemented with MAGIC and fabricated through the MOSIS service. The completed IC was tested and evaluated using a specially designed binary to multivalued logic converter and decoder. Engineering modifcations to the original current mode inverter cells used by HAMLET were made leading to significant power savings in a complete design. The fabricated device performed as predicted by SPICE simulation. Exhaustive functional testing produced correct steady-state output signals for all cases of input loadings. Finally, we show HAMLET minimization heuristics are not efficient in the design of adder cells by comparison with an alternative modulo 4 carry save adder cell in current mode CMOS.
Type
Thesis
Description
Series/Report No
Department
Electrical Engineering
Computer Science
Organization
Identifiers
NPS Report Number
Sponsors
Funder
Format
93 p.
Citation
Distribution Statement
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.