Naval Postgraduate School
Dudley Knox Library
NPS Dudley Knox Library
View Item 
  •   Calhoun Home
  • Theses and Dissertations
  • 1. Thesis and Dissertation Collection, all items
  • View Item
  •   Calhoun Home
  • Theses and Dissertations
  • 1. Thesis and Dissertation Collection, all items
  • View Item
  • How to search in Calhoun
  • My Accounts
  • Ask a Librarian
JavaScript is disabled for your browser. Some features of this site may not work without it.

Browse

All of CalhounCollectionsThis Collection

My Account

LoginRegister

Statistics

Most Popular ItemsStatistics by CountryMost Popular Authors

The design of a predictive read cache

Thumbnail
Download
Icondesignofpredicti00robe.pdf (9.320Mb)
Download Record
Download to EndNote/RefMan (RIS)
Download to BibTex
Author
Robert, Joseph R., Jr.
Date
1996-03
Advisor
Fouts, Douglas J.
Second Reader
Terman, Frederick W.
Metadata
Show full item record
Abstract
The objective of this research has been the creation of a hardware design for a Predictive Read Cache (PRC). The PRC is a developmental cache intended to replace second-level caches common in modern microprocessor systems. The PRC has the potential of being faster and cheaper than current second-level caches and is distinctive in its ability to predict data addresses to be referenced by a central processing unit. Previous research has analyzed the behavior that the PRC must exhibit. During the described research, the behavior was modeled in the Verilog hardware description language. Verilog-XL was used for simulation, which uses the Verilog behavioral model as input. The behavioral model suggests that the internal structure of the PRC could be divided into six modules, each performing part of the function of the whole PRC. Each of these blocks was studied for hardware equivalents, easing the development of the total structural model. Using Verilog structural models as input, Epoch was used to automatically perform a very large-scale integrated (VLSI) circuit layout and to generate timing information. The Epoch output files are used for further simulation with Verilog-XL to identify critical parts of the design. The result of this research is a complete hardware design for the PRC.
Rights
This publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. Copyright protection is not available for this work in the United States.
URI
http://hdl.handle.net/10945/8236
Collections
  • 1. Thesis and Dissertation Collection, all items

Related items

Showing items related by title, author, creator and subject.

  • Thumbnail

    DRFM CORDIC processor and sea clutter modeling for enhancing structured false target synthesis 

    Ang, Pak Siang (Monterey, California: Naval Postgraduate School, 2017-09);
    In this thesis, we investigate two critical components of a digital-image synthesizer electronic warfare architecture that can be used to infuse false targets into high-range resolution profiling radars. The first investigation ...
  • Thumbnail

    A FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATION OF A COGNITIVE RADAR TARGET RECOGNITION SYSTEM 

    Sessions, Calvin A. (Monterey, California. Naval Postgraduate School, 2021-09);
    The objective of this study is to design a field-programmable gate array (FPGA) implementation of a cognitive radar (CRr) target recognition system for electronic warfare applications. This thesis expands on the ...
  • Thumbnail

    EXPLORING CUSTOM HARDWARE TO ACCELERATE A PROGRAM BY LEVERAGING PARALLELISM 

    Davis, Javen E. (Monterey, CA; Naval Postgraduate School, 2021-06);
    It is essential that computer science students learn how to leverage parallelism to accelerate their applications due to the dramatic slowing of sequential CPU performance. One way that computer scientists can leverage ...
NPS Dudley Knox LibraryDUDLEY KNOX LIBRARY
Feedback

411 Dyer Rd. Bldg. 339
Monterey, CA 93943
circdesk@nps.edu
(831) 656-2947
DSN 756-2947

    Federal Depository Library      


Start Your Research

Research Guides
Academic Writing
Ask a Librarian
Copyright at NPS
Graduate Writing Center
How to Cite
Library Liaisons
Research Tools
Thesis Processing Office

Find & Download

Databases List
Articles, Books & More
NPS Theses
NPS Faculty Publications: Calhoun
Journal Titles
Course Reserves

Use the Library

My Accounts
Request Article or Book
Borrow, Renew, Return
Tech Help
Remote Access
Workshops & Tours

For Faculty & Researchers
For International Students
For Alumni

Print, Copy, Scan, Fax
Rooms & Study Spaces
Floor Map
Computers & Software
Adapters, Lockers & More

Collections

NPS Archive: Calhoun
Restricted Resources
Special Collections & Archives
Federal Depository
Homeland Security Digital Library

About

Hours
Library Staff
About Us
Special Exhibits
Policies
Our Affiliates
Visit Us

NPS-Licensed Resources—Terms & Conditions
Copyright Notice

Naval Postgraduate School

Naval Postgraduate School
1 University Circle, Monterey, CA 93943
Driving Directions | Campus Map

This is an official U.S. Navy Website |  Please read our Privacy Policy Notice  |  FOIA |  Section 508 |  No FEAR Act |  Whistleblower Protection |  Copyright and Accessibility |  Contact Webmaster

Export search results

The export option will allow you to export the current search results of the entered query to a file. Different formats are available for download. To export the items, click on the button corresponding with the preferred download format.

A logged-in user can export up to 15000 items. If you're not logged in, you can export no more than 500 items.

To select a subset of the search results, click "Selective Export" button and make a selection of the items you want to export. The amount of items that can be exported at once is similarly restricted as the full export.

After making a selection, click one of the export format buttons. The amount of items that will be exported is indicated in the bubble next to export format.