The design of a predictive read cache

Abstract

The objective of this research has been the creation of a hardware design for a Predictive Read Cache (PRC). The PRC is a developmental cache intended to replace second-level caches common in modern microprocessor systems. The PRC has the potential of being faster and cheaper than current second-level caches and is distinctive in its ability to predict data addresses to be referenced by a central processing unit. Previous research has analyzed the behavior that the PRC must exhibit. During the described research, the behavior was modeled in the Verilog hardware description language. Verilog-XL was used for simulation, which uses the Verilog behavioral model as input. The behavioral model suggests that the internal structure of the PRC could be divided into six modules, each performing part of the function of the whole PRC. Each of these blocks was studied for hardware equivalents, easing the development of the total structural model. Using Verilog structural models as input, Epoch was used to automatically perform a very large-scale integrated (VLSI) circuit layout and to generate timing information. The Epoch output files are used for further simulation with Verilog-XL to identify critical parts of the design. The result of this research is a complete hardware design for the PRC.