Development of a new prediction algorithm and a simulator for the Predictive Read Cache (PRC)

Abstract

Efforts to bridge the cycle-time gap between high-end microprocessors and low-speed main memories have led to a hierarchical approach in memory subsystem design. The predictive read cache (PRC) has been developed as an alternative way to overcome the speed discrepancy without incurring the hardware cost of a second-level cache. Although the PRC can provide an improvement over a memory hierarchy using only a first-level cache, previous studies have shown that its performance is degraded due to the poor locality of reference caused by program branches, subroutine calls, and context switches. This thesis develops a new prediction algorithm that allows the PRC to track the miss patterns of the first-level cache, even with programs exhibiting poor locality. It presents PRC design alternatives and hardware cost estimates for the implementation of the new algorithm. The architectural support needed from the underlying microprocessor is also discussed. The second part of the thesis involves the development of a memory hierarchy simulator and an address-trace conversion program to perform trace-driven simulations of the PRC. Using address traces captured from a SPARC-based computer system, the simulations show that the new prediction algorithm provides a significant improvement in the PRC performance. This makes the PRC ideal for embedded systems in space-based, weapons-based and portable/mobile computing applications.