Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes

Abstract

The design and evaluation of several different low-power, high-speed, high-density complementary gallium arsenide (CGaAs) dynamic logic families that are compatible with existing CGaAs fabrication processes and design tools are documented. Circuits studied include Domino logic, N-P Domino logic and Two-Phase Dynamic FET Logic (TPDL). The TPDL circuits have been implemented and fabricated. The dynamic circuits are evaluated and compared with typical static logic circuits for speed, power consumption and layout area. Dynamic circuits are non-ratioed logic. Therefore, the transistor sizes can be minimized to reduce the layout area and the power dissipation of the circuits. Furthermore, dynamic circuits are faster than static circuits because they do not use PFETs for evaluation, only for precharging. Dynamic circuits consume less power than the static circuits because they have no short-circuit current and a reduced leakage current (only switching current flows in the dynamic circuits). This means that CGaAs dynamic logic circuits have higher speed than Directly-Coupled FET Logic (DCFL) and lower power consumption than complementary GaAs logic.