Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes
dc.contributor.advisor | Fouts, Douglas J. | |
dc.contributor.author | Shehata, Khaled Ali | |
dc.date | September 1996 | |
dc.date.accessioned | 2012-08-09T19:22:01Z | |
dc.date.available | 2012-08-09T19:22:01Z | |
dc.date.issued | 1996-09 | |
dc.identifier.uri | http://hdl.handle.net/10945/8639 | |
dc.description.abstract | The design and evaluation of several different low-power, high-speed, high-density complementary gallium arsenide (CGaAs) dynamic logic families that are compatible with existing CGaAs fabrication processes and design tools are documented. Circuits studied include Domino logic, N-P Domino logic and Two-Phase Dynamic FET Logic (TPDL). The TPDL circuits have been implemented and fabricated. The dynamic circuits are evaluated and compared with typical static logic circuits for speed, power consumption and layout area. Dynamic circuits are non-ratioed logic. Therefore, the transistor sizes can be minimized to reduce the layout area and the power dissipation of the circuits. Furthermore, dynamic circuits are faster than static circuits because they do not use PFETs for evaluation, only for precharging. Dynamic circuits consume less power than the static circuits because they have no short-circuit current and a reduced leakage current (only switching current flows in the dynamic circuits). This means that CGaAs dynamic logic circuits have higher speed than Directly-Coupled FET Logic (DCFL) and lower power consumption than complementary GaAs logic. | en_US |
dc.description.uri | http://archive.org/details/lowpowerhighspee109458639 | |
dc.format.extent | 258 p. | en_US |
dc.language.iso | en_US | |
dc.publisher | Monterey, California. Naval Postgraduate School | en_US |
dc.rights | Copyright is reserved by the copyright owner | en_US |
dc.title | Low-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processes | en_US |
dc.type | Thesis | en_US |
dc.contributor.corporate | Naval Postgraduate School | |
dc.contributor.department | Department of Electrical and Computer Engineering | |
dc.subject.author | GaAs | en_US |
dc.subject.author | Dynamic logic | en_US |
dc.subject.author | CHIGFET | en_US |
dc.subject.author | CGaAs | en_US |
dc.subject.author | Two-phase dynamic FET logic | en_US |
dc.subject.author | TPDL | en_US |
dc.subject.author | Clock generator | en_US |
dc.subject.author | Domino logic | en_US |
dc.subject.author | N-P domino logic | en_US |
dc.subject.author | CLA | en_US |
dc.subject.author | Static logic | en_US |
dc.description.service | Lieutenant Colonel, Egyptian Air Force | en_US |
etd.thesisdegree.name | Ph.D. in Electrical and Computer Engineering | en_US |
etd.thesisdegree.level | Doctoral | en_US |
etd.thesisdegree.discipline | Electrical Engineering | en_US |
etd.thesisdegree.discipline | Computer Engineering | en_US |
etd.thesisdegree.grantor | Naval Postgraduate School | en_US |
dc.description.distributionstatement | Approved for public release; distribution is unlimited. |
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