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dc.contributor.advisorFouts, Douglas J.
dc.contributor.authorShehata, Khaled Ali
dc.dateSeptember 1996
dc.date.accessioned2012-08-09T19:22:01Z
dc.date.available2012-08-09T19:22:01Z
dc.date.issued1996-09
dc.identifier.urihttp://hdl.handle.net/10945/8639
dc.description.abstractThe design and evaluation of several different low-power, high-speed, high-density complementary gallium arsenide (CGaAs) dynamic logic families that are compatible with existing CGaAs fabrication processes and design tools are documented. Circuits studied include Domino logic, N-P Domino logic and Two-Phase Dynamic FET Logic (TPDL). The TPDL circuits have been implemented and fabricated. The dynamic circuits are evaluated and compared with typical static logic circuits for speed, power consumption and layout area. Dynamic circuits are non-ratioed logic. Therefore, the transistor sizes can be minimized to reduce the layout area and the power dissipation of the circuits. Furthermore, dynamic circuits are faster than static circuits because they do not use PFETs for evaluation, only for precharging. Dynamic circuits consume less power than the static circuits because they have no short-circuit current and a reduced leakage current (only switching current flows in the dynamic circuits). This means that CGaAs dynamic logic circuits have higher speed than Directly-Coupled FET Logic (DCFL) and lower power consumption than complementary GaAs logic.en_US
dc.description.urihttp://archive.org/details/lowpowerhighspee109458639
dc.format.extent258 p.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsCopyright is reserved by the copyright owneren_US
dc.titleLow-power high-speed dynamic logic families for complementary gallium arsenide (CGaAs) fabrication processesen_US
dc.typeThesisen_US
dc.contributor.corporateNaval Postgraduate School
dc.contributor.departmentDepartment of Electrical and Computer Engineering
dc.subject.authorGaAsen_US
dc.subject.authorDynamic logicen_US
dc.subject.authorCHIGFETen_US
dc.subject.authorCGaAsen_US
dc.subject.authorTwo-phase dynamic FET logicen_US
dc.subject.authorTPDLen_US
dc.subject.authorClock generatoren_US
dc.subject.authorDomino logicen_US
dc.subject.authorN-P domino logicen_US
dc.subject.authorCLAen_US
dc.subject.authorStatic logicen_US
dc.description.serviceLieutenant Colonel, Egyptian Air Forceen_US
etd.thesisdegree.namePh.D. in Electrical and Computer Engineeringen_US
etd.thesisdegree.levelDoctoralen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.disciplineComputer Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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