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dc.contributor.advisorFouts, Douglas J.
dc.contributor.advisorPace, Phillip E.
dc.contributor.authorLuke, Brian L.
dc.dateDecember 2004
dc.date.accessioned2012-08-22T15:30:35Z
dc.date.available2012-08-22T15:30:35Z
dc.date.issued2004-12
dc.identifier.urihttp://hdl.handle.net/10945/9908
dc.description.abstractThis dissertation investigates a mixed-signal, electronic warfare (EW) system-on-a-chip (SoC) design capable of synthesizing false radar returns in response to imaging radar interrogations that, when integrated into the range-Doppler processing, form an image of a false target. Detailed designs for the EW SoC components including the false target digital image synthesizer (DIS) and a novel analog to digital converter (ADC) are provided in this research. Alternative DIS architectures are presented that reduce circuit die area and power dissipation. This research also describes the theory, design, implementation, simulation, and testing of a proof-of-concept application-specific integrated circuit (ASIC) providing automatic counterflow-clock pipeline skew control for the DIS. High performance ADCs are key components of mixed-signal SoCs. Design and simulation results for an 8-bit 1 GS/s robust symmetric number system (RSNS) folding ADC are presented. The gray-code properties of the RSNS make it desirable for error control and low-power ADC implementations. A complete mathematical description of the N-modulus RSNS redundancies is discovered, which results in closed-form expressions for the longest sequence of unique RSNS vectors for moduli of the form m - 1, m, and m +1, as well as an efficient search algorithm for N-modulus systems at least six orders of magnitude faster than previously published results. Lastly, an N-modulus RSNS-to-binary converter design procedure and a circuit design for an 8-bit, 4-modulus 1 GS/s RSNS-to-binary converter are presented.en_US
dc.description.urihttp://archive.org/details/architectureofni109459908
dc.format.extentxxii, 296 p. : ill. (some col.) ; 28 cm.en_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsUpon consultation with NPS faculty, the School has determined that this dissertation may be released to the public and that its distribution is unlimited, effective January 25, 2011.en_US
dc.subject.lcshElectronics in military engineering.en_US
dc.titleArchitecture of an integrated microelectronic warfare system on a chip and design of key componentsen_US
dc.typeThesis
dc.typeThesis
dc.contributor.departmentNaval Postgraduate School (U.S.)
dc.subject.authorFolding ADCen_US
dc.subject.authorgray-code propertiesen_US
dc.subject.authordynamic rangeen_US
dc.subject.authorresidue number systemen_US
dc.subject.authorrobust sym-metric number systemen_US
dc.subject.authorinverse synthetic aperture radaren_US
dc.subject.authorelectronic warfareen_US
dc.subject.authorsystem-on-a-chipen_US
dc.subject.authorwideband imaging radaren_US
dc.subject.authordigital image synthesisen_US
dc.subject.authorradar countermeasuresen_US
dc.subject.authoranti-ship ca-pable missileen_US
dc.subject.authorcounterflow clock pipelineen_US
dc.subject.authorautomatic clock skew controlen_US
etd.thesisdegree.namePh.D. in Electrical Engineeringen_US
etd.thesisdegree.levelDoctoralen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate School (U.S.)en_US
dc.description.distributionstatementApproved for public release; distribution is unlimited.


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