Temperature distribution and thermally induced stresses in electronic packages
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This investigation is concerned with the steady state temperature and thermally induced stress distributions in electronic packages due to heat generated by the chip. Finite Element codes were employed to solve for the distribution of temperature and stresses within the package. Four parametric studies were undertaken to determine their effects on system behavior. The material study considered two chip and two solder materials and four substrate materials. Convective heat transfer was varied from 200 W/m C through 500 W/m "C. In the geometric study, chip height to overall height was varied. The effect of package encapsulation was studied. Results are presented for both temperature and stress distributions at the solder interfaces.
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