Design of a pipelined multiplier using a Silicon Compiler

Abstract

This thesis describes the design methodology and the process of employing the GENESIL Silicon Compiler (GSC)(Version 7.1) in the layout of a pipelined multiplier, in 1.5 micron CMOS technology, using a parallel multiplier cell array. Additionally, background material on the theory of multiplication, as well as the concept and theory of pipelining are presented. The results revealed two practical limits of the GSC system which precluded achieving the high component density made possible by full custom manual CAD methods using graphic layout tools. Although the GSC system did not perform as desired in this study, it offers a viable alternative to the labor intensive, full custom, Very Large Scale Integration graphic layout tools in use today.