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dc.contributor.advisorDouglas J. Fouts
dc.contributor.advisorFrederick Terman.
dc.contributor.authorChristensen, Kathryn S.
dc.date.accessioned2013-05-06T18:43:56Z
dc.date.available2013-05-06T18:43:56Z
dc.date.issued1998-06
dc.identifier.urihttp://hdl.handle.net/10945/32687
dc.description.abstractThis work is part of an ongoing effort to bridge the cycle time gap between high speed processing units and low speed main memories through the use of memory hierarchies. Cache memory exploits the principle of locality by providing a small, fast memory between the processor and the main memory. The Predictive Read Cache (PRC) further improves the overall memory hierarchy performance by tracking the data read miss patterns of memory accesses, developing a prediction for the next access and prefetching the data into the faster cache memory. The PRC has been proven to significantly improve system performance when acting as a second level cache. The purpose of this thesis is to simulate the effectiveness of the PRC as a first level cache in the memory hierarchy using the same simulator developed to prove the effectiveness of the PRC as a second level cache.en_US
dc.description.urihttp://archive.org/details/architecturaldev1094532687
dc.format.extentxiv, 79 p.;28 cm.en_US
dc.language.isoen_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsApproved for public release, distribution unlimiteden_US
dc.titleArchitectural development and performance analysis of a primary data cache with read miss address prediction capabilityen_US
dc.title.alternativeNAen_US
dc.typeThesisen_US
dc.contributor.secondreaderNA
dc.contributor.departmentElectrical Engineering
dc.subject.authorNAen_US
dc.description.recognitionNAen_US
dc.description.serviceU.S. Navy (U.S.N.) author.en_US
etd.thesisdegree.nameM.S. in Electrical Engineeringen_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US


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