Architectural development and performance analysis of a primary data cache with read miss address prediction capability

Abstract

This work is part of an ongoing effort to bridge the cycle time gap between high speed processing units and low speed main memories through the use of memory hierarchies. Cache memory exploits the principle of locality by providing a small, fast memory between the processor and the main memory. The Predictive Read Cache (PRC) further improves the overall memory hierarchy performance by tracking the data read miss patterns of memory accesses, developing a prediction for the next access and prefetching the data into the faster cache memory. The PRC has been proven to significantly improve system performance when acting as a second level cache. The purpose of this thesis is to simulate the effectiveness of the PRC as a first level cache in the memory hierarchy using the same simulator developed to prove the effectiveness of the PRC as a second level cache.