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dc.contributor.advisorPace, Phillip E.
dc.contributor.authorTong, Kee Leong
dc.date.accessioned2012-03-14T17:43:45Z
dc.date.available2012-03-14T17:43:45Z
dc.date.issued2010-12
dc.identifier.urihttp://hdl.handle.net/10945/4970
dc.descriptionApproved for public release; distribution is unlimiteden_US
dc.description.abstractThe need to realize pervasive battlespace awareness is placing an increasing demand on the bandwidth and resolution performance of modern sensors, communication receivers and electronic warfare. Fundamental to realizing this demand is the omnipresent highspeed analog-to-digital converters. The need constantly exists for converters with lower power consumption. To reduce the number of power-consuming components, high-performance ADCs employ parallel configuration of analog folding circuits to symmetrically fold the input signal prior to quantization by high-speed comparators. In this thesis, a prototype of an optical folding 6-bit ADC utilizing a 7-bit preprocessing architecture was implemented using the Robust Symmetrical Number System (RSNS). The RSNS preprocessing architecture is a modular scheme in which the integer values within each modulus (comparator states), when considered together, change one at a time at the next position i.e. Gray-code property. MATLAB simulations are used to help determine the properties of the RSNS. These properties include the dynamic range (largest number of distinct consecutive vectors) and the location of the dynamic range within the number system. Since the waveform repeats every fundamental period, a method that reduces all indexes to the 'lowest common denominator' is developed to find the symmetrical residues of each channel. Using the symmetrical residues determined, the corresponding DC shifts on each waveform can be calculated. The architecture employs a three-modulus (mod 7, 8, 9) scheme to preprocess the antenna signal. Electro-optic modulation of the input signal to generate the required number of folds within the dynamic range was successfully carried out in the three-modulus realization using modulators with a small half-wave voltage. The detection output are carefully aligned and postprocessed before amplitude analyzing with a high-speed comparator circuit responsible for the sampling and quantization of the signal (designed under a separate thesis). Low frequency analysis of the results using a 1 kHz input signal indicate a 5.42 effective number of bits (ENOB), a signal-to-noise ratio plus distortion (SINAD) of 34.42 dB, and a total harmonic distortion (THD) of -- 62.84 dB.en_US
dc.description.urihttp://archive.org/details/photonicnalogtod109454970
dc.format.extentxvi, 87 p. : col. ill. ;en_US
dc.publisherMonterey, California. Naval Postgraduate Schoolen_US
dc.rightsThis publication is a work of the U.S. Government as defined in Title 17, United States Code, Section 101. As such, it is in the public domain, and under the provisions of Title 17, United States Code, Section 105, may not be copyrighted.en_US
dc.subject.lcshElectronics in military engineeringen_US
dc.titlePhotonic analog-to-digital converters preprocessing using the robust symmetrical number system for direct digitization of antenna signalsen_US
dc.typeThesisen_US
dc.contributor.secondreaderJenn, David C.
dc.contributor.corporateNaval Postgraduate School (U.S.)
dc.contributor.departmentElectrical Engineering
dc.description.serviceRepublic of Singapore Air Force authoren_US
dc.identifier.oclc698386726
etd.thesisdegree.nameM.S.en_US
etd.thesisdegree.levelMastersen_US
etd.thesisdegree.disciplineElectrical Engineeringen_US
etd.thesisdegree.grantorNaval Postgraduate Schoolen_US
etd.verifiednoen_US


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